nRF51 Architecture Overview

At the heart of the nRF51 architecture are the 32-bit industry standard ARM Cortex-M0 processor and the 2.4GHz Multi-protocol radio transceiver which supports a range of protocols including Bluetooth low energy, ANT, and proprietary 2.4GHz RF protocols. The popular low-power cost-effective ARM Cortex-M0 CPU has a relatively fast start-up time (around 2.5us) and a fast duty cycling which leads to a boosted Bluetooth device responsiveness. In addition to that, Flash/RAM memories are embedded in the same chip die. The nRF51 SoC has also a good set of hardware peripherals as we will see in the next section. The nRF51 SoCs offer a great value for money, the cost of these SoCs on wholesale is in the range of 2$ per chip ( 2019 ). As can be seen in the block diagrams below and throughout this lesson, you are getting a lot for that money.  This architecture has been around since 2012 and its quite mature and had without doubt a great success in the market. It’s recommended when cost is the main constraint in your Bluetooth-enabled project, and support for Bluetooth 5 features is not needed.

nRF51 Architecture
nRF51 Block Diagram-Brief

System Blocks & Peripherals Blocks

Available system blocks and peripherals in the nRF51 architecture are summarized below, these peripherals are the core of the nRF5x family and can be found also in the nRF52 series with some enhancements ( For instance, The RADIO peripheral on an the nRF52 series has; in addition to the 1Mbps Bluetooth Low Energy physical layer ( 1M BLE PHY) found in the nRF51; a high speed BLE physical layer  (2M BLE PHY) and a long range BLE physical layer ( CODED BLE PHY – nRF52840 Only) ).

nRF51 Block Diagram-Detailed
  • General-Purpose Input/Output (GPIO): One GPIO peripheral with up to 32 individual pins that can be configured with pull-up or pull-down resistors. Very fixable block to interact with external hardware components. GPIO hardware, and available hardware abstraction layer is studied in Lesson7.
  • GPIO tasks and events (GPIOTE): The GPIO Tasks and Events (GPIOTE) block provides functionality for accessing GPIO pins using tasks and events registers (Without the CPU intervention), which is a great performance/power feature as we will see in following lessons. Hands-on exercises on the GPIOTE are covered in great depth in  Lesson10 .
  • Programmable Peripheral Interconnect (PPI): The Programmable Peripheral Interconnect (PPI) is a core system block which enables different peripherals to interact autonomously with each other using tasks and events and without having to use the CPU ( For performance/power optimization ). Covered in details in Lesson9 with hands-in exercise.
  • 2.4 GHz Radio (RADIO): This is the core peripheral responsible for the SoC wireless connectivity, and probably the main reason why you are considering the nRF5x SoC in the first place.The RADIO contains a 2.4 GHz radio transmitter/receiver. (No Blutooth5 hardware support, No 2M BLE PHY and No CODED BLE PHY on the nRF51). We will put this peripheral under the microscope in the Intermediate Level of this course.
  • Timer/counter (TIMER): The TIMER block is frequently used and is very handy in many situations where precise hardware timing is required. It can operate in two modes, Timer mode and Counter mode. We will dive into its hardware and available hardware abstraction layers, drivers in Lesson8.
  • Real Time Counter (RTC):  This system block is used to maintain timing on the system. Do not confuse this system block with Real-time clock which is also abbreviated by RTC. The RTC on an nRF5x SoC is a 24 bit low-frequency counter with frequency prescaling, tick, compare, and overflow events support. Think about it as a low-resolution low power timer.  This system block is used intensively in the Intermediate Level of this course in conjunction with the SoftDevice. In addition for using it with the SoftDevice, the RTC is used by many other libraries and modules this is why we have several RTC hardware on chip. The RTC uses very little power while running, and is therefore used to supervise sleep duration and to wake the CPU after a certain amount of time. It’s worth noting that this system block operate on the low power LFCLK clock source and hence the low power.
  • Watchdog timer (WDT): Very useful block to detect and recover from various system failures.The watchdog is implemented as a down-counter that generates a TIMEOUT event when it wraps over after counting down to 0. This system block also uses the low-frequency clock source (LFCLK).
  • Random Number Generator (RNG): The Random Number Generator (RNG) generates true non-deterministic random numbers based on internal thermal noise. Used in the security layer of communication stacks. You may think of these types of peripherals as as cryptographic co-processors.
  • Temperature sensor (TEMP): The temperature sensor is an on-chip sensor that measures the silicon die temperature. Range -25C to +75C with resolution of 0.25 degree. The TEMP is experimented with the UART in Lesson12 to send the temperature of the die to a host computer through UART.
  • AES Electronic Codebook mode encryption (ECB): AES ECB is a single AES block encrypt hardware module, it supports 128 bit AES encryption. Again, these types of peripherals are cryptographic co-processors.
  • AES CCM Mode Encryption (CCM): This system block is used intensively by the security layer of the Bluetooth stack ,The AES CCM supports three operations: key-stream generation, packet encryption, and packet decryption. All these operations are done in compliance with the Bluetooth specification.
  • Accelerated Address Resolver (AAR): More cryptographic hardware support blocks.
  • Serial Peripheral Interface (SPI) Master :  An interface bus widely used to transfer data to/from external chips and small peripherals such as, sensors, and SD cards. It supports multiple slaves.
  • SPI Slave (SPIS): The slave implementation of the SPI.
  • I2C compatible Two Wire Interface (TWI) :  Interface protocol intended to allow multiple slave chips to communicate with one or more master chips. Used widely to interface with sensors and actuators.
  • Universal Asynchronous Receiver/Transmitter (UART): The UART implements support for the following features: Full-duplex operation, Automatic flow control, Parity checking and generation for the 9th data. We will cover this peripheral and available hardware abstraction layers, drivers and libraries (serial library ) in-depth in Lesson11.
  • Quadrature Decoder (QDEC): The Quadrature Decoder (QDEC) can be used for decoding the output of an off-chip quadrature encoder.
  • Analog to Digital Converter (ADC): 10-bit incremental Analog to Digital Convertor with 8 channels sampling.
  • Low Power Comparator (LPCOMP): It compares an input voltage against a reference voltage. This comparator is frequently used  as an analog wakeup source from System OFF or System ON sleep modes.

Clock Resources

The nRF51 series chips can source the system clocks from a range of internal or external high and low frequency oscillators and distribute them internally to peripherals and system blocks based upon a module’s individual requirements. This prevents large clock trees from being active and drawing power when system blocks/peripherals needing this clock reference are not active. If a  firmware enables a module that needs a clock reference without the corresponding oscillator running, the clock management system inside an nRF51 SoC will automatically enable the RC oscillator option and provide the clock. When the system block/peripheral goes back to idle, the clock management will automatically set the oscillator to idle. To avoid delays involved in starting a given oscillator, or if a specific oscillator is required, the firmware can override the automatic oscillator management so it keeps oscillators active when no system modules require the clock reference ( This feature is called Low Latency and is discussed with depth  in Lesson 14 ).

nrf51422 Tutorial
Available Clocking In The nRF51

HFCLK stands for High Frequency Clock , while the LFCLK stands for Low Frequency Clock. The choice of clock sourcing is configurable in the firmware and it impacts power consumption and accuracy.

Note that the HFCLK source is needed by the CPU, RADIO, and almost all units in the system except the RTC and WDT. The RTC and WDT operate on a low power, high accuracy clock which is the LFCLK . The RTC uses very little power while running, and is therefore used to supervise sleep duration and to wake the CPU after a certain amount of time. The RTC is also used intensively by the SoftDevice to maintain precise protocol timing.

Example: The nRF51-DK Development Kit, which host the nRF51422 SoC has two external crystal oscillators. The default master one is the 16Mhz which is the one always connected to the SoC and used by the CPU and most system blocks and peripherals. The second crystal is the  32Khz low frequency crystal oscillator that is used by the RTC and the WDT peripherals.


nRF1-DK schematic
nRF51 Development Kit (DK) – Available oscillators highlighted

The reason why the 32Khz low frequency crystal oscillator is marked as optional is because it can be derived internally or synthesized  from the 16Mhz source using a synthesizer as shown in the figure below , however this configuration will impact the power consumption and accuracy negatively.

nRF51 tutorial
The CLOCK system block in the nRF51 series

Memory Layout

In the nRF51 architecture, there are three main types of memories:

  • Code memory. This is a Non-volatile Flash memory (Code FLASH) where your firmware and communication stack will be stored.
  • Random Access Memory ( Data RAM ). This is for things like the stack, heap, static data, RADIO, Crypto, and other resources buffers.
  • Peripheral registers (PER). Memory-mapped registers of the different peripherals and system blocks in the system.

In addition, there is one information block (FICR) containing read only parameters describing configuration details of the device and another information block (UICR) that can be configured by the user.

All memory blocks and system blocks/peripherals registers are mapped in a common memory map as illustrated in the figure below :

nRF51 Memory Map

The Data RAM ( Address 0x2000 0000 ) is divided into blocks for separate power management schemes which is controlled by the power management system block. Each block is divided into two 4 kByte RAM sections with separate RAM AHB slaves. The power management block can be configured to allow certain blocks of RAM to be retained during different sleep modes, which gives finer control over memory power consumption.

nRF51 Tutorial
nRF51 Data RAM Organization


Available Chips Options

There are four SoC chips options in the nRF51 series :

nRF51 Series tutorial
nRF51 Series
nRF51 tutorials
nRF51 Chips Options – In Details

Hardware peripherals wise, all these chips have almost the same hardware peripherals with some minor differences, However, when it comes to the supported short-range protocols (Bluetooth low energy, ANT) they differ as follows:

The nRF51822 supports only Bluetooth low energy. The nRF51824 is simply the automotive grade of the nRF51822 and also only support Bluetooth low energy.

On the other hand, the nRF51422 supports both ANT and Bluetooth low energy protocols.

Finally, the nRF51802 is a low cost implementation of the nRF51822. The low prices comes at the expense of a higher current consumption and weaker radio reception compared to the nRF51822.

The nRF51 series does not support Bluetooth 5.

Full comparison of the nRF51 SoCs is shown below

nRF51822 tutorials
nRF51 SoCs – In-Depth Comparison(Click to enlarge)

All documentation related to the nRF51 SoCs, such as Production Specifications( equivalent to IC datasheet ), Product Change Notification (PCNs), Informational Notice (INs), and Product Anomaly Notification(PANs) are available for each SoC in the nRF51 series on Nordic Semiconductor infocenter.

nRF51 tutorial
nRF51 SoCs documentation organized per SoC on Nordic Semiconductor infocentor

Common hardware and software architecture among the different chips and consistent peripheral addressing making these chips easy to work with as we will see in the Lesson 6 – The Unified Peripheral Architecture . It’s also worth noting that the core registers and registers for tasks, events, shorts and interrupts have equal offsets for all peripherals.

Advanced features:

The features listed below are actually present across all nRF5x family (Both nRF51 and nRF52) and they facilitate the ultra low power capabilities on the nRF5x family , as we will see in the next lessons and tutorials.

  1. PPI ( Programmable Peripheral Interconnect ):  A network of buses and switches that  allow different peripherals/system blocks to interact with each other independent of the CPU . This saves power by minimizing processor active time and at the same time relaxes real time requirements for the processor. See illustrations below:
PPI Illustration – Programmable Peripheral Interconnect Bus
PPI Illustration – Peripherals using PPI while CPU is asleep
PPI Illustration – Tasks and Events registers in the peripherals allow to automate tasks among peripherals with minimum CPU intervention
PPI Illustration – Tasks and Events registers in the peripherals allow to automate tasks among peripherals with minimum CPU intervention


2. Flexible GPIO:  It allows the digital interfaces of the peripherals to be mapped to most pins available on the SoC. This feature is achieved using an embedded pin crossbar . This has a huge advantage in reducing the complexity of the PCB of the device or the development board. See illustration below:

Flexible GPIO Illustration – The problem with fixed pins interfaces
Flexible GPIO Illustration – Pin crossbar simplifies PCB routing
Flexible GPIO Illustration – Pin crossbar allows interface mapping to most pins
Flexible GPIO Illustration – Flexible GPIO leads to reduced PCB complexity


3. Automated power management: This is a quite sophisticated unit and one of the main factors why an nRF5x SoC can be powered by a coin-cell battery for up to years. The purpose of this unit is to minimize active modules and minimize peak and average current. With automated power management, peripherals only use power when they need power.

Automated power management Illustration – Only needed modules are powered and clocked

There are two explicit sleep modes that a developer can put the nRF5 SoC into. They are called System On and System Off.

In System On sleep mode, which is the one commonly used, the CPU can be put explicitly to sleep ( through user-friendly APIs provided by the nRF5 SDK Power Management Library , which internally uses the ARM assembly instructions of SEV,  and WFE  )  as we will see in Lesson14. In System On the needed peripherals can still be interacting with each other and the memory using the PPI and EasyDMA respectively (Covered next). In System On mode, the CPU can be woken up using interrupts or events that are configured to trigger interrupts. At the same time, The automated power management unit is actively maintaining the usage of power of the system blocks and peripherals .In System On, the expected current consumption of the SoC is in the order of few micro amperes.

The other sleep mode is System Off, this is the deepest power saving mode the SoC can enter. In this mode, the CPU, system’s core functionality, system blocks, and peripherals are powered down and all ongoing tasks are terminated. In this mode, the CPU can only wake up on GPIO DETECT signal , or LPCOMP ANADETECT (voltage input crossing a certain value). The system always resets after waken up from a System Off sleep mode.  In System Off, the expected current consumption of the SoC is in the order of  sub-micro amperes( several hundreds of nano amperes).

Power management on the nRF5 SoC is the focus of Lesson14.

4. EasyDMA (Built-in DMA inside the peripherals ): The EasyDMA significantly eliminate CPU involvement in frequent data transfer operations, which saves power by minimizing CPU active time, and at the same time relaxes real time requirements for the CPU. The acronym EasyDMA stands for Easy Direct Memory Access. Direct Memory Access is a common hardware in most CPU architectures, however, the Easy here stands for a DMA which is built-in the peripheral itself and not as a DMA hardware which is shared among all system blocks and peripherals. Example the RADIO peripheral has an EasyDMA which is inside it (and not shared with any other peripheral), which allows the RADIO to read/write to RAM without the CPU involvement. Note that there are other peripherals on the nRF51 that has built-in DMA (EasyDMA): Serial Peripheral Interface(SPI) ,and the ECB. This feature was taking to the extreme in the nRF52 and was added inside even more peripherals.

EasyDMA inside the RADIO peripheral Illustration

In other words, while the PPI feature allows peripherals to interact to each other autonomously, the EasyDMA allows the peripherals to interact with memory (RAM) autonomously. One of the main strategics followed by Nordic Semiconductor to reduce power consumption is to offload processing from the CPU as much as possible and put it into sleep. Both the PPI and EasyDMA can help in that significantly as we will see in the next lessons.

nRF51 Development Boards

Listed below are the official nRF51 development boards By Nordic Semiconductor. They are recommended to be used in the initial development phase, and prototyping of your nRF51-based project.

nRF51-DK (nRF51422) : The nRF51 DK is a single-board development board  that has the following key features:

  • Hosts the nRF51422 SoC.
  • All GPIO and interfaces available at edge connectors.
  • Buttons and LEDs for user interaction.
  • I/O interface for Arduino form factor plug-in modules.
  • SEGGER J-Link OB Debugger with debug out functionality.
  • Virtual COM Port interface via UART.
  • Drag and drop Mass Storage Device (MSD) programming.
  • mbedOS enabled (We will talk about this in Lesson4).
  • Accepts power through:
    • USB.
    • External source (1.8V-3.6V).
    • Single 2032 coin-cell battery, onboard battery holder.

The board ID of the nRF51-DK is PCA10028 .

nRF51-DK Board (PCA10028) tutorial
nRF51-DK Development Kit
nRF51-DK PINS Layout

nRF51-Dongle (nRF51422)  :  This is a USB Stick form factor development board, used widely as a BLE sniffer and for debugging/testing with the nRF Connect for Desktop program. Key features of this dongle:

  • Hosts the nRF51422 SoC.
  • RGB LED.
  • 6 solder pads for GPIO/interface connections.
  • Supports nRFSniffer – Bluetooth Smart protocol sniffing firmware.
  • Supports Master Emulator – Bluetooth Smart Peer connection firmware(For use with nRF Connect for Desktop).
  • All I/O and interfaces available via connectors.
  • USB drag and drop programming and USB Virtual COM port for serial terminal.
  • Segger J-Link and CMSIS-DAP interface for programming and debugging from offline tools and pyOCD.
  • Connector for RF measurements.
  • Pins for power consumption measurements.
  • mbedOS enabled(We will talk about this in Lesson4).
  • Accepts power through:
    • USB.
    • External source (1.8V-3.6V).

The Board ID for the nRF51-Dongle is PCA10031

nRF51 Dongle
nRF51-Dongle Tutorial
nRF51-Dongle PINS Layout

Enroll to the to the Nordic nRF5x BLE In-Depth Training Course (Foundation Level) to access full materials.

References and pictures:
Nordic Semiconductor
ARM Mbed