This is a comprehensive hands-on training course for embedded systems design based on the Xilinx All Programmable SoC (Zynq-7000 SoC) family of system on chips. It covers key fundamental principles of embedded systems design including: Memory-Mapped I/O, Hardware Design Flow, Customized Hardware Integration, Interrupts, Hardware Timers, DMA and Animation , Data Logging using SD Cards, ADC/DAC and Digital Audio Processing, Stepper Motor Controller, Networked Systems, and Embedded Operating Systems. The course is divided into eleven labs:
- Lab1) Memory-Mapped I/O: Builds a solid foundation on the tools used in the development (Vivado Design Suite 2015.2 and SDK). A software application is developed in C to initialize and configure GPIO IPs to display a binary count on LEDs. It continuously read the push buttons status and control the direction and speed of LED’s blinking according to the button being pressed.
- Lab2) Hardware Design Flow: Continues to lay the groundwork for Vivado, however, it focuses mainly on hardware design flow, which involves among many steps: specification, design, simulation, and verification. The same exact counter’s specifications of Lab1 is implemented but completely in hardware (PL-side only) using Verilog Hardware Description Language.
- Lab3) Customized Hardware Integration: Goes in depth in hardware design by taking an inside look on the implementation of an open-source customized memory-mapped peripheral controller (OLED Display Controller) and its driver. Different aspects of I/O interface circuitry of the controller will be examined, including the control circuits and the data registers. The SPI protocol and drivers’ development are also covered in this lab.
- Lab4) Interrupts: Studies the Zynq SoC’s interrupt structure, and focuses on the Generic Interrupt Controller (GIC). The procedures needed to implement an interrupt-driven system are explained in details. An interrupt-driven application is developed with detailed interrupt handlers (ISRs) and interrupt setup functions.
- Lab5) Hardware Timers: Examines the rich set of hardware timers available on the Zynq chip and their appropriate usages. The AXI-Timer is selected as a case study, which is added to the PL-side of the chip. The timer will be utilized to generate a precise periodic interrupt every one second, which is used in implementing a real time clock.
- Lab6) DMA and Animation: Sheds the light on how to transfer mass amount of data into or out of memory without processor intervention. There are several Direct Memory Controllers available on the Zynq chip, the one we are interesting in is the DMAC. The DMAC is available in the PS-side of the chip. Steps needed to initiate a DMA transfer are covered. An application is developed that utilizes DMAC to transfer bitmaps frames of a certain character(Alex the alien) into the display controller memory region (The OLED screen displays Alex moving around ( In animation)). Another application to control Alex using the push buttons is developed as well.
Lab7) Data Logging using SD Cards: All non-volatile memories available on the Zedboard are studied. The focus is on the SD,its controller SD/SDIO,and its driver. An application is implemented to use the SD card to store a string of characters in the format “HH:MM:SS Event: Sensor X Triggered #” every time the central push button on the Zedboard is pressed (the push button is emulating a sensor), HH:MM:SS represents the real time. The FatFs – FAT (File Allocation Table) File System Library and its API is also covered in details.
- Lab8) ADC/DAC and Digital Audio Processing: Provides an introduction on Analog-to-Digital Converters, Digital-to-Analog Converters (DAC), sampling, and quantization basics. The ADAU1761 audio codec chip (coder-decoder) available on the Zedboard is used for audio processing. The codec is configured through I2C bus, which is also covered in depth. An application is develop that uses the two ADC of the codec to sample stereo audio (Right channel + Left channel) at 48Khz. The digitalized samples is sent to the Zynq chip through the I2S standard audio bus for processing. On the Zynq chip, a dedicated hardware called NCO (Numerically Controlled Oscillator) is responsible for generating samples of sine wave at selected frequencies. These samples of sine wave is superpositioned on the received audio samples. The modified audio samples (received audio samples + sine wave samples) is sent over the I2S bus to the DAC convertors of the codec for playing on an earphone connected to the line out port of the chip. I2S standard audio bus is examined as well.
- Lab9) Stepper Motor Controller: Basics of a Bipolar Stepper Motors structure is provided. The PmodSTEP – by Digilent is used as a sister-board to electrically drive a stepper motor (Bipolar ,1.8 Degree,0.33A,12V). The sister-board is connected through external Pmod connector of Zedboard. The necessary external connections and physical constraints needed to connect an external component to Zedboard are outlined and explained. An application is developed to control the motor direction and speed through the 5 push buttons on Zedboard.
- Lab10) Networked Systems: Teaches how to get a Zynq chip connect to an Ethernet network and expand its capabilities to include network capabilities. The Lightweight IP (lwIP) is utilized to add a TCP/IP networking stack. An application is developed to send messages to be displayed on the OLED display screen through a webpage running on a host computer. The HTTP 1.1 protocol and HTML are also discussed in this lab.
- Lab11) Embedded Operating Systems: Explains the benefits of using an operating system on an embedded system, and reasons for using it. A brief on Linux kernel architecture is given with deep focus on device drivers and device models. The Linux kernel is configured,built,and downloaded as a system image on the Zedboard SD card to target the ARM Cortex-A9. The Toolchains(compilers ,assemblers ,linker and debuggers) are also discussed in this lab.
A Brief on the Zynq-7000 SoC:
The Zynq All programmable SoC consists of an ARM Cortex A9 dual core processing system(PS) which includes various dedicated peripherals as well as a configurable programmable logic (PL). This integration of the two makes the Zynq an embedded platform with high level of flexibility. The hardware architecture is shown below. Three possible ways this platform can be used:
1. The Zynq PS can be used independently of the PL.
2. Customized hardware (Soft IP) may be added in the PL and connected to extend the functionality of the PS. You can use this PS + PL combination to achieve complex and efficient design on the SoC.
3. Logic in the PL can be designed to operate independently of the PS. However the PS or JTAG must be used to program the PL.